Search - hdb3 vhdl

[ELanguage] hdb3

Description: 在VHDL平台上实现HDB3编码的源程序已调试完
Platform: | Size: 1337 | Author: 王晓鹏 | Hits:

[Other resource] hdb3

Description: HDB3码的VHDL实现共三个模块：插入V、插入B以及单双极性变换
Platform: | Size: 1178 | Author: Xingzhi | Hits:

[Other resource] hdb3 decoder

Description: 我上期做的VHDL设计方案，用于在FPGA或CPLD中实现HDB3的编码-I do view on the VHDL design options for the CPLD or FPGA to achieve HDB3 code
Platform: | Size: 119678 | Author: 王薇 | Hits:

Description: 源于老师的作业,实现将01代码转化成HDB3码,另外还有用VHDL语言编的,不过我这没有-teachers from the operations, achieving 01 HDB3 code into the code, as well as using VHDL series, but I am not
Platform: | Size: 39011 | Author: 王原 | Hits:

[Communication] 各种码型变换

Description: 基于vhdl语言的各种码型变换，包括AMI、HDB3、CMI BPH、RZ、BNRZ等。
Platform: | Size: 2322 | Author: guowenting | Hits:

[Communication] HDB3code

Description: 光纤通信中的编码方式hdb3，编解码的vhdl实现-Optical fiber communications in encoding hdb3, codec realize the VHDL
Platform: | Size: 5120 | Author: 江泽民 | Hits:

[VHDL-FPGA-Verilog] test02

Description: 用quartusII编写的，基于vhdl语言的按键加法器，从0到11，也可通过拨码开关控制，从11到0，加入了键盘防手抖。-QuartusII prepared to use, based on the VHDL language button adder, from 0-11, also available via dial code switch control, from 11-0, joined the anti-tremor keyboard.
Platform: | Size: 204800 | Author: zhg | Hits:

[VHDL-FPGA-Verilog] hdb3

Description: 实现了用vhdl语言完成在编码过程中的插B功能，-vhdl hdb3
Platform: | Size: 1024 | Author: 王英超 | Hits:

[VHDL-FPGA-Verilog] HDB3encoder

Description: 数字基带信号的传输是数字通信系统的重要组成部分。在数字通信中，有些场合可不经过载波调制和解调过程，而对基带信号进行直接传输。采用AMI码的信号交替反转，有可能出现四连零现象，这不利于接收端的定时信号提取。而HDB3码因其无直流成份、低频成份少和连0个数最多不超过三个等特点，而对定时信号的恢复十分有利，并已成为CCITT协会推荐使用的基带传输码型之一。为此，本文利用VHDL语言对数据传输系统中的HDB3编码器进行了设计。-Digital baseband signal transmission is an important digital communication system components. In digital communications, some occasions may, after modulation and demodulation process, and on the base-band signals transmitted directly. AMI code using the turn signal inversion, there may be zero Silian phenomenon, which is not conducive to the receiving end of the timing signal extraction. HDB3 code and its non-DC components, and even less low-frequency components of 0 up to more than three the number of characteristics such as timing signals for the recovery of very favorable, and the Association has become the CCITT recommended base-band transmission-type, one code. In this paper, the use of VHDL language in the data transmission system HDB3 encoder has been designed.
Platform: | Size: 108544 | Author: shashou | Hits:

[Other] CPLD_FPGA

Description: 基于VHDL的通信原理课程设计详细资料，HDB3 AMI PCM PAM的编译码-VHDL
Platform: | Size: 7461888 | Author: xiaobo | Hits:

[VHDL-FPGA-Verilog] vhdl_hdb3

Description: a VHDL source code on HDB3 encoder realaized in FPGA/CPLD
Platform: | Size: 1024 | Author: xiaominjin | Hits:

[VHDL-FPGA-Verilog] hdb3_decode

Description: hdb3码的编码及解码代码，包括模块连接。-hdb3 code encoding and decoding code, including modules.
Platform: | Size: 651264 | Author: Gina | Hits:

[VHDL-FPGA-Verilog] hdb3_codedecode

Description: 用VERILOG实现的，hdb3编码器和解码器，经过前仿真和后仿真成功-Achieved with the VERILOG, hdb3 encoder and decoder, after a successful pre-simulation and post simulation
Platform: | Size: 435200 | Author: Along | Hits:

[SCM] ys

Description: 两路单极性HDB3+和HDB3-信号，经映射模块后完成单极性到双极性信号的数字转化，该模块由设计文件ys.v完成。由于映射后得到的是双极性归零码，通过该模块得到双极性非归零码。该模块由设计文件delay.v完成-Two unipolar HDB3-signals HDB3+, and by the mapping module to complete unipolar to bipolar signal digital conversion, the module completed by the design documents ys.v. As the map is obtained by bipolar zero code, through the module are bipolar NRZ. The module is completed by the design documents delay.v
Platform: | Size: 1024 | Author: 筱筱 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 基于 VHDL平台的NRZ码转HDB3码程序-NRZ-> HDB3 coding based on VHDL
Platform: | Size: 1024 | Author: 高达 | Hits:

[VHDL-FPGA-Verilog] HDB3(2)

Description: 利用vhdl编写实现数字基带传输HDB3码解码程序-vhdl hdb3 decode
Platform: | Size: 2048 | Author: kid | Hits:

[VHDL-FPGA-Verilog] HDB3

Description: hdb3键盘接口VHDL程序，经过严格仿真，很有参考价值。-HDB3 VHDL keyboard interface program, after a rigorous simulation, of great reference value.
Platform: | Size: 260096 | Author: 崔凯华 | Hits:

[VHDL-FPGA-Verilog] HDB3-VHDL-code

Description: HDB3的VHDL语言描述，注释在文件内-HDB3 source code in VHDL
Platform: | Size: 264192 | Author: 冰凝 | Hits:

[VHDL-FPGA-Verilog] HDB3

Description: 按照要求对“数字基带信号HDB3译码器设计与建模”进行逻辑分析，了解HDB3译码器译码原理，了解各模块电路的逻辑功能，设计通信系统框图，画出实现电路原理图，编写VHDL语言程序，上机调试、仿真，记录实验结果波形，对实验结果进行分析。(In accordance with the requirements of the logical analysis of the design and modeling of the digital baseband signal HDB3 decoder, HDB3 decoder principle, understand the logic function of each module circuit diagram, communication system design, draw the circuit principle diagram, VHDL language program, debugging, simulation, experimental results recorded waveform, the analysis of experimental results.)
Platform: | Size: 8990720 | Author: Remrinrin | Hits:

[VHDL-FPGA-Verilog] EDA

Description: 本设计是在Quartus ii开发环境下采用VHDL语言实现的AMI/HDB3编码器课程设计。(This design is a course design of AMI / HDB3 encoder implemented by VHDL language in the development environment of Quartus II.)
Platform: | Size: 1916928 | Author: Z Yu | Hits:

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[ELanguage] hdb3

[Other resource] hdb3

[Other resource] hdb3 decoder

[Other resource] HDB3

[Communication] 各种码型变换

[Communication] HDB3code

[VHDL-FPGA-Verilog] test02

[VHDL-FPGA-Verilog] hdb3

[VHDL-FPGA-Verilog] HDB3encoder

[Other] CPLD_FPGA

[VHDL-FPGA-Verilog] vhdl_hdb3

[VHDL-FPGA-Verilog] hdb3_decode

[VHDL-FPGA-Verilog] hdb3_codedecode

[SCM] ys

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] HDB3(2)

[VHDL-FPGA-Verilog] HDB3

[VHDL-FPGA-Verilog] HDB3-VHDL-code

[VHDL-FPGA-Verilog] HDB3

[VHDL-FPGA-Verilog] EDA

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